1. Field of the Invention
The present invention relates to an apparatus for generating a control signal used in a recording device for recording a digital information signal on a digital recording medium. More particularly, it relates to an apparatus for generating a control signal concerning selection of a channel word to be recorded on an information track of a digital recording medium, in a recording device for recording channel words on information tracks in the magnetic recording medium, in which information words have (n+1) bits. Each of the information words, which has a one-bit digital word affixed thereto, is converted into an (n+1)-bit channel word by using precoders.
2. Background of the Related Art
A typical 8 mm video tape recording system records a recording signal together with a pilot signal on each recording track of a recording medium, in order to accurately control the recording tracks. However, a method for recording pilot signals which simply have different frequencies, together with recording signals is inefficient in terms of efficiently using the recording medium. This is because pilot signals in neighboring tracks should be located sufficiently far from a pilot signal in a track to be reproduced, in order not to cause crosstalk in the frequency domain, with the pilot signal.
To solve the above problem, a high-efficiency encoding technology is disclosed in U.S. Pat. No. 5,142,421 to Kahlman et al., issued on Aug. 25, 1992, entitled "Device For Recording A Digital Information Signal On A Record Carrier." This reference is described in detail below with reference to FIGS. 1 and 2.
FIG. 1 shows a device for recording a digital information signal on a recording carrier, which is referred to in the above reference. In FIG. 1, a first affixing unit 100 affixes a "0" to successive n-bit information words input via an input terminal 10, and a second affixing unit 150 affixes a "1" to successive n-bit information words. First and second precoders 200 and 250 convert the (n+1)-bit information words into (n+1)-bit channel words, respectively. The output of first precoder 200 is supplied to a control signal generator 300 and a first delay 500, and the output of second precoder 250 is supplied to control signal generator 300 and a second delay 550.
The control signal generator 300, shown in detail in FIG. 2 and described later in detail, generates a control signal CS using the supplied data. The control signal CS is supplied to first and second precoders 200 and 250 and also to a multiplexer 600. The first and second delays 500 and 550 delay the input data until control signal generator 300 generates a control signal corresponding to the input data. The multiplexer 600 selects one of the signals output from first and second delays 500 and 550 according to the control signal CS, and supplies the selected signal to a recording unit 700. The first and second precoders 200 and 250 operate to contain identical data in internal memories in response to control signal CS. For example, when the output data of first precoder 200 is transmitted to recording unit 700, the data contained in first precoder 200 is supplied to second precoder 250, with the result that first and second precoders 200 and 250 contain identical data.
FIG. 2 is a detailed block diagram of control signal generator 300 shown in FIG. 1. Control signal generator 300 includes, as shown in FIG. 2, a spectrum analysis circuit 301 which receives the signal output from first precoder 200, and a spectrum analysis circuit 302 which receives the signal output from second precoder 250. The spectrum analysis circuits 301 and 302 have the same structure, and accordingly, only spectrum analysis circuit 301 is shown in detail in FIG. 2. The spectrum analysis circuit 301 shown in detail in FIG. 2 is substantially the same as those shown in FIG. 17 of U.S. Pat. No. 5,142,421, except for an adder 311, an integrator 312 and a square wave generator 35. Since differences between the spectrum analysis circuit 301 of FIG. 2 and that of the FIG. 17 circuit of the above reference can be fully understood by one skilled in the art, the detailed description of the differences are omitted.
The spectrum analysis circuit 301 includes three spectrum component detectors, i.e., a peak detector 310 for detecting a peak component in which a particular frequency component is larger than a set reference value, a notch detector 320 for detecting a notch component capable of discriminating whether the particular frequency component is smaller than the set reference value, and a dip detector 330 for detecting a dip component assisting peak detection by attenuating the signal by a certain amount around the peak component. Peak detector 310, notch detector 320 and dip detector 330 detect, respectively, the peak, notch and dip components from the "0"-affixed channel word. An adder 340 sums signals output from detectors 310, 320 and 330. A spectrum analysis circuit 302 performs the same operation as that of the spectrum analysis circuit 301, except with respect to a "1"-affixed channel word. A comparator 303 compares the output signals of spectrum analysis circuits 301 and 302, to thereby generate the control signal CS.
Since the above adder 340 receives the five signals and sums all these signals, construction of the circuit is complicated. Also, an accurate result cannot be obtained unless relative gains are the same when each spectrum is estimated. Further, since the complicated circuit lengthens processing time, a digital circuit having a negative feedback loop requires a high-speed operational device to complete the negative feedback loop within a certain amount of time.